module Registers (reset,ena, addra, dataa,
    enb, addrb, datab, enc, addrc, datac);
    
    // Input
    input [0:0] reset;
    input [0:0] ena;
    input [4:0] addra;
    input [0:0] enb;
    input [4:0] addrb;
    input [0:0] enc;
    input [4:0] addrc;
    input [31:0] datac;

    // Output
    output reg [31:0] dataa;
    output reg [31:0] datab;
    
    // Registers
    reg [31:0] Registers [31:0];

    
    always @(negedge(reset)) begin

        Registers[0] = 32'b0;
        Registers[1] = 32'b0;
        Registers[2] = 32'b0;
        Registers[3] = 32'b0;
        Registers[4] = 32'b0;
        Registers[5] = 32'b0;
        Registers[6] = 32'b0;
        Registers[7] = 32'b0;
        Registers[8] = 32'b0;
        Registers[9] = 32'b0;
        Registers[10] = 32'b0;
        Registers[11] = 32'b0;
        Registers[12] = 32'b0;
        Registers[13] = 32'b0;
        Registers[14] = 32'b0;
        Registers[15] = 32'b0;
        Registers[16] = 32'b0;
        Registers[17] = 32'b0;
        Registers[18] = 32'b0;
        Registers[19] = 32'b0;
        Registers[20] = 32'b0;
        Registers[21] = 32'b0;
        Registers[22] = 32'b0;
        Registers[23] = 32'b0;
        Registers[24] = 32'b0;
        Registers[25] = 32'b0;
        Registers[26] = 32'b0;
        Registers[27] = 32'b0;
        Registers[28] = 32'b0;
        Registers[29] = 32'b0;
        Registers[30] = 32'b0;
        Registers[31] = 32'b0;

    end    
        

    always @(ena or enb or enc or
        addra or addrb or addrc or
        dataa or datab or datac) begin

        if ((ena == 1'b1) && (addra < 32)) begin
            dataa = Registers[addra];
        end

        if ((enb == 1'b1) && (addrb < 32)) begin
            datab = Registers[addrb];
        end
        
        if ((enc == 1'b1) && (addrc < 32)) begin
            Registers[addrc] = datac;
        end
    
    end
    
endmodule
